1. Field of the Invention
This invention relates generally to a class of non-volatile memory devices referred to as flash electrically erasable programmable read-only memory (flash EEPROM). More particularly, this invention relates two-transistor flash EEPROM cells and arrays. Even more particularly this invention relates to methods and means to read, program, and erase digital data from a two-transistor flash EEPROM cell to improve endurance of the flash EEPROM cell.
2. Description of Related Art
The structure and application of the flash EEPROM is well known in the art and illustrated in “Technical Comparison of Floating Gate Reprogrammable Nonvolatile Memories,” (SST White Paper) staff, Silicon Storage Technology, Inc., November, 2001 Technical Paper, found May 7, 2002 www.sst.com. The Flash EEPROM provides the density advantages of an erasable programmable read-only memory (EPROM) that employs ultra-violet light to eliminate the programming with the speed of a standard EEPROM. FIG. 1a illustrates a cross-sectional view of a stacked gate flash EEPROM cell of the prior art. The stacked gate flash EEPROM cell is formed within a p-type substrate 10. An n+ drain region 12 and an n+ source region 14 are formed within the p-type substrate 10.
A relatively thin gate dielectric 16 is deposited on the surface of the p-type substrate 10. The thin gate dielectric 16 is also referred to as a tunneling oxide. A poly-crystalline silicon floating gate 18 is formed on the surface of the gate dielectric 16 above the channel region 20 between the drain region 12 and source region 14. An interpoly dielectric layer 22 is placed on the floating gate 18 to separate the floating gate 18 from a second layer of poly-crystalline silicon that forms a control gate 24.
The source region 14 is connected to a source voltage generator through the source line 30. The control gate 28 is connected through the word line 28 to the word line voltage generator. And the drain region 12 is connected through the bit line 24 to the bit line voltage generator.
According to conventional operation, the flash EEPROM cell is programmed by setting the word line voltage generator to a relatively high voltage (on the order of 10V). The bit line voltage generator is set to a moderately high voltage (on the order of 5V), while the source line voltage generator is set to the ground reference potential (0V).
With the voltages as described above, hot electrons will be produced in the channel 20 near the drain region 12. These hot electrons will have sufficient energy to be accelerated across the gate dielectric 16 and trapped on the floating gate 18. The trapped hot electrons will cause the threshold voltage of the field effect transistor (FET) that is formed by the flash EEPROM cell to be increased by three to five volts. This change in threshold voltage by the trapped hot electrons causes the cell to be programmed.
To erase the flash EEPROM cell a moderately high positive voltage (on the order of 5V) is generated by the source line voltage generator. Concurrently, the word line voltage generator is set to a relatively large negative voltage (on the order of −10V). The substrate 10 is set to the ground reference potential. The bit line voltage generator is usually disconnected from the bit line 26 to allow the drain region 12 to float. Under these conditions there is a large electric field developed across the tunneling oxide 16 in the source region 14. This field causes the electrons trapped in the floating gate 18 to flow to portion of the floating gate 18 that overlaps the source region 16. The electrons are then extracted to the source region 14 by the Fowler-Nordheim tunneling.
The flash EEPROM functions based on the electronic charge stored on the floating gate 18 sets the memory transistor to a logical “1” or “0”. Depending on whether the memory structure is an enhancement or depletion transistor when the floating gate is neutral or contains electrons (negative charge), the memory cell will or will not conduct during read. When the floating gate 18 is neutral or has an absence of negative charge, the memory cell will conduct during read. The conducting or nonconducting state is output as the appropriate logical level. In the memory cell as shown the word line voltage generator and the control gate 28 is set to the voltage level of the power supply voltage source. The substrate 10 and the source line voltage generator and thus the source 14 are set to the level of the ground reference voltage. The bit line voltage generator and the drain 12 are set to a small voltage level sufficient to cause a small current to conduct in the bit line 26. The small current is detected by a sense amplifier connected to the bit line 26 to detect the presence or absence of the electronic charge and therefore the digital data stored on the flash EEPROM cell. If the floating gate 18 has an electronic charge, the threshold voltage of the memory cell increases and the memory cell does not conduct at the voltage level of the power supply voltage source and the sense amplifier detects a logical “1.” Alternately, if there is no electronic charge present on the floating gate 18, the memory cell turns on and the sense amplifier detects a logical “0.”
As further described in the SST White Paper and illustrated in U.S. Pat. No. 6,314,022 (Kawata, et al.), U.S. Pat. No. 6,265,266 (Dejenfelt, et al.), U.S. Pat. No. 6,212,102 (Georgakos, et al.), U.S. Pat. No. 5,912,842 (Chang, et al.), and U.S. Pat. No. 5,612,913 (Cappelletti, et al.) a two-transistor thin oxide cell has a select transistor added to the cell to further control the read, program, and erase of the flash EEPROM cell. Refer now to FIG. 1b for an illustration of a two-transistor thin oxide flash EEPROM cell with a select transistor of the prior art. The source of the select transistor is formed of the drain 12 of the memory cell. The drain of the select transistor is formed of the n+ region 32. A layer of poly-crystalline silicon is placed over the thin oxide layer 16 between the source region 12 and the drain region 32 of the select transistor to form the control gate 34 of the select transistor. The control gate 34 is connected to a gate select line 36. The gate select line allows the control of the application of the higher voltages to the memory cell when the flash EEPROM cell is being selected or not selected and thus helps mitigate the effects of the higher voltages on the memory cell.
A split gate flash EEPROM cells, as shown in FIG. 1c, is described in the SST White Paper and illustrated in U.S. Pat. No. 6,212,100 (Choi), U.S. Pat. No. 6,103,576 (Deustcher, et al.), U.S. Pat. No. 6,034,892 (Choi), U.S. Pat. No. 5,859,454 (Choi, et al.), U.S. Pat. No. 5,852,577 (Kianian, et al.). The split gate flash EEPROM cell is formed within a p-type substrate 50. An n+ drain region 52 and an n+ source region 54 are formed within the p-type substrate 50.
A relatively thin gate dielectric 56 is deposited on the surface of the p-type substrate 50. A poly-crystalline silicon floating gate 58 is formed on the surface of the gate dielectric 56 above the channel region 60 between the drain region 52 and source region 54. An interpoly dielectric layer 62 is placed on the floating gate 58 to separate the floating gate 58 from a second layer of poly-crystalline silicon that forms a control gate 64. A field enhancing tunneling injector 63 is formed on the floating gate 58 to assist in erasure of the split gate EEPROM cell. The control gate 64 is formed in stepped fashion having a portion resting on the interpoly dielectric 62 above the floating gate 58 and another portion resting directly upon the gate dielectric 56 essentially forming a two-transistor memory cell as shown in FIG. 2. In FIG. 2, the split gate transistor is represented by the select transistor Txs 72 and the memory transistor Txm 74. The portion of the split gate EEPROM cell representing the select transistor 72 is the region where the control gate 64 is placed on the gate dielectric 56. The portion of the split gate EEPROM cell representing the memory transistor 74 is the region where the control gate is resting upon the interpoly dielectric 62 above the floating gate.
The source region 54 is connected to a source voltage generator through the source line 70. The control gate 68 is connected through the word line 68 to the word line voltage generator. And the drain region 52 is connected through the bit line 66 to the bit line voltage generator.
The split gate flash EEPROM cell is programmed as described in “The Impacts of Control Gate Voltage on the Cycling Endurance of Split Gate Flash Memory,” (Huang, et al.), IEEE Electron Device Letters, VOL. 21, NO. 7, July 2000, pp. 359–361, by setting the word line voltage generator to a moderate positive voltage (on the order of 2V). The bit line voltage generator is set to a relatively low positive voltage (on the order of 0.5V), while the source line voltage generator is set to a relatively high positive voltage (on the order of 50V).
With the voltages as described above, hot electrons will be produced in the channel 60 near the source region 54. These hot electrons will have sufficient energy to be accelerated across the gate dielectric 56 and trapped on the floating gate 58. The trapped hot electrons will cause the threshold voltage of the field effect transistor (FET) that is formed by the flash EEPROM cell to be increased by three to five volts. This change in threshold voltage by the trapped hot electrons causes the cell to be programmed.
To erase the flash EEPROM cell the word line voltage generator is set to a relatively large negative voltage (on the order of −11.0v–−13.0v). The source line voltage generator, the bit line voltage generator and the substrate 50 is set to the ground reference potential. Under these conditions there is a large electric field developed across the inter poly dielectric 62. This field causes the electrons trapped in the floating gate 58 to flow to portion of the floating gate 58 in the region of the field enhancing tunneling injector 63. The electrons are then extracted to the control gate 64 by the Fowler-Nordheim tunneling.
The read operation of the split gate flash EEPROM has the word line voltage generator set to approximate the voltage level of the power supply voltage source (on the order of 3.0V) and the bit line voltage generator set to the relatively moderate voltage level sufficient to cause a current to be sensed by sense amplifiers present on the bit line 66. As described above, the charge present on the floating gate 64 determines the threshold voltage of the split gate flash EEPROM cell and whether the data discerned by the sense amplifier is a logical “1” or a logical “0.”
“Reliability Considerations for Reprogrammable Nonvolatile Memories,” (SST Reliability Paper), staff, Silicon Storage Technology, Inc., November, 2001 Technical Paper found May 7, 2002 www.sst.com, describes the basic failure categories that effect EEPROM cell. The basic failure categories are read faults, retention faults, and endurance faults. The failure rates for read faults and retention faults in the present technologies are sufficiently low that expected failures are in the 100's to 1000's of years and are approaching the intrinsic failure rate of the materials. Thus, the major failure category is the endurance fault.
Endurance is the ability of a flash EEPROM cell to meet its data sheet specifications as a function of accumulated program and erasure cycles over time. The data sheet specifications include write functionality, data retention, and read access time. The endurance faults encompass nine major types. Endurance faults, unlike other MOS reliability concerns, result even though the device is operated within the data sheet limits. The endurance faults occur because the insulators of the gate dielectric and the interpoly dielectric are subjected to electrical stress from the Erase and Programming operations. The basic endurance failure mechanisms are oxide damage and charge trapping caused by the cumulative effects of passing a current through the oxide and placing a high electric field across the oxide. The basic endurance fault modes are:                1. A stuck bit where a bit is unable to change and can be stuck in either logic state. A stuck bit can be caused either by charge trapping or oxide rupture.        2. Retention Degradation where the loss of charge of the floating gate is caused by either trapped charge or damage in the insulating oxide.        3. Read Time Degradation is the gradual increase in the read access time caused by accumulated trapped charge or gradual charge loss reducing the cell current.        4. Erase Time Degradation is the gradual increase in the time required to erase the memory caused by accumulated trapped charge.        5. Program Time Degradation is the gradual increase in the time required to program the memory caused by accumulated trapped charge.        6. Disturbs are an intrinsic phenomena of all memory arrays. A disturb occurs when reading, erasing, or programming one location causes an unwanted alteration at another location.        7. Over erase occurs where device is unable to Read or Program correctly because of excessive memory transistor source to drain current, which grounds the bit line read or programming voltage.        8. Erase Disturb occurs by unintentionally changing the contents in a non-accessed location, while erasing another location. This occurs because the high voltage required to erase may not be isolated from the non-accessed locations.        9. Program Disturb occurs by unintentionally changing the contents in a non-accessed location, while programming another location. This occurs because the high voltage required to Program may not be isolated from the non-accessed locations.        
U.S. Pat. No. 5,329,487 (Gupta, et al.) describes a two transistor flash EPROM cell. The two-transistor flash EPROM cell includes a first floating gate transistor for programming the cell and a second merged transistor for reading the cell. The first transistor, a floating gate transistor, has a drain coupled to the write bit line, a gate coupled to the word line, and a source coupled to the source line. The merged transistor effectively consists of a floating gate transistor connected to the floating gate of the first transistor and in series with a NMOS enhancement transistor. The series NMOS transistor has a voltage threshold of about 1 to 2 volts, thus preventing cell activation caused by over erasure (negative voltage threshold) of the floating gate transistor.
U.S. Pat. No. 4,403,307 (Maeda) illustrates an EEPROM cell composed of two double gate type field effect transistors, which each have control gate and floating gate. The structures of the two field effect transistors are essentially identical to that of the stacked gate EEPROM cell as described in FIG. 1a. The sources of the two transistors are commonly connected to a source line, which is connected as described above to a source line voltage generator. The control gates of the two transistors are commonly connected to the word line, which is connected to the word line voltage generator. One of the drains of the two transistors is connected to a read bit line and the drain of the other transistor is connected to a write bit line. The two floating gates are connected such that charge placed on the floating gate of the transistor connected to the write bit line is placed on the floating gate of the transistor of the read bit line.
The reading of the EEPROM cell of Maeda is accomplish through the read bit line voltage generator and sense amplifier connected to the read bit line. The writing of the EEPROM cell of Maeda is accomplished through the write bit line voltage generator connected to the write bit line. Erasure of the EEPROM cell is accomplished with irradiating the cell with ultraviolet light or other radiation.